Pre-Si Validation Engineer

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November 04

Job description

Develops pre-silicon functional validation tests to verify system will meet design requirements.

Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests

Analyzes and uses results to modify testing.

The candidate will work as a member of a verification team playing a key leading role in developing IPs.

The responsibilities will include but not be limited to:

Create review and signoff verification test plans.

Develop the architecture and design of the verification environment in UVM.

Development of test plans test bench BFMs checkers monitors trackers scoreboard and functional coverage.

Develop run debug tests in SystemVerilog.

Ownership of verification of block/ cluster in IPs.

Drive and participate in verification code functional coverage RTL code coverage reviews and provide implement feedback across the project.

Contribute to the development and maintenance of long-term design verification strategy.

Track progress of the block/ cluster owned to achieve goals timely.Be able to work with teams across org/ geos.

Master of Science (or a Master of Technology) degree in Electrical Engineering with more than four years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than six years of relevant industry experience out of which at least 4 years of hands-on IP verification experience using SV and UVM

Proficiency in SV, UVM, and object-oriented programming

Strong understanding of verification principles

Proven track record in IP verification from environment development to tests development to validation closure

Excellent written and verbal communication skills

Very good at creation of test plans schedules and cost estimates for design verification efforts

Experience in the development and deployment of verification strategies and methodologies across teams and organizations is added advantage

Apart from simulation should have work experience with at least one other verification aspect like formal verification, gate Level verification, etc.

Knowledge of I2C, I3C, SPI, UART, IOSF, AXI, DMAs, Mailboxes; will be added advantage.

Proficiency in scripting languages and utilities including Make Perl Python etc.Expert-level knowledge of simulation tools such as VCS from Synopsys.


Skill & Language
Electrical engineering
formal verification
1 - 3 years
1 candidate
December 06
Full Time
Senior Mgmt.
Tutong District
Intel33 jobs · Tutong District
Public Company
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